The Aspex Q Semiconductor IP (SIP) Compression Engine is available for license as a stand-alone block, which can be integrated into a custom ASIC or ASSP implementation for specific applications, such as:

• Wireless HDMI chipsets
• PC Graphics chipsets
• HD Camcorders
• Digital Still Cameras
• Webcams

Available as fully synthesizable Verilog RTL, the inherent scalability of the Q architecture allows it to be easily scaled to support any price, power, performance or quality point required for your applications.

At the heart of the Q architecture is our 8th generation ASProCore, a SIMD architecture optimised for pixel- and macroblock-level processing functions, such as transforms, intra-prediction, sub-pel motion estimation & deblocking. The number of Macroblock Processing Units in the Q can be easily be scaled up or down to accomodate any desired performance.

The compression engine can also be configured with optional flexible hardware accelerators for motion estimation and entropy coding.

Software running in the Q's Control Unit can implement a wide range of codecs, including

• H.264 / AVC (Baseline, Main and/or High Profiles)
• Scalable Video Codec (SVC)
• MPEG-2
• MPEG-4 Part 2 (Advanced Simple Profile)
• AVS
• Flash (On2 VP6)
• Motion JPEG
• JPEG-2000

With industry-leading die size and power, the Q IP provides a futureproof, flexible media processing engine for video encoding.

To find out more about licensing the Aspex Compression Engine for your application, please contact us directly.