At the heart of Aspex’s Q processor and its predecessors is the ASProCore – Aspex’s unique parallel processing fabric. Associative String Processing (ASP) is a fine-grain Single Instruction, Multiple Data (SIMD) parallel processing architecture.

ASP architectures are ideal for taking advantage of the natural parallelism present in many computing tasks, such as image processing and digital signal processing. Aspex’s implementation of the ASP architecture is known as ASProCore, and is an ultra fine-grained implementation which squeezes many thousands of simple Processing Elements onto a single chip. Data I/O takes place in parallel with vector processing via a dedicated high-bandwidth dual-port memory interface. Memory bandwidth scales with the number of processing elements, to ensure that processing power is balanced with input/output capability.

Simple programming model
The ASProCore array sits alongside an on-chip RISC CPU core, and appears as a memory-mapped co-processor, accelerating demanding data-parallel tasks such as image processing or digital signal processing. Program code executes on the on-chip RISC CPU, which feeds parallel instructions to the ASProCore co-processor to perform vector processing operations. The single-processor architecture is independent of the number of processors in the ASProCore array.
This provides for simplicity of programming and easy scalability both on- and off-chip.

Scalable, One-dimensional “String” topology
With ASP, all the Processing Elements are connected in a one-dimensional line, or “string”, communicating using a high-speed linear inter-processor communications network. A 1-dimensional string topology has some significant advantages when compared to traditional 2D array or grid processors, namely:

• Simple uni-processor programming model
• Easy to connect multiple processors together to form a longer string
• Advantages in silicon efficiency and ease of design

How long is a piece of string?
An ASProCore array can, in principle, have any number of processing elements in the string. This scalability can be exploited in two ways:

• Cascading multiple chips together to dial up “performance on demand”
• Implementing chips in new, smaller silicon geometries to pack more processing elements per square millimeter

Provided that the amount of input data exceeds the number of Processing Elements, ASProCore can deliver a close-to-linear performance increase as the number of processors increases.

Intuitive, scalable Associative addressing model
The thousands of individual Processing Elements in each Linedancer chip are all connected in a Single Instruction, Multiple Data configuration. This means that they each receive the same instruction from the embedded RISC CPU. With traditional SIMD architectures, this limits the usefulness of the array, as conditional (IF-THEN-ELSE) constructs would either be processed sequentially or would require data to be swapped in and out of the array, using up valuable memory bandwidth. ASProCore’s Associative addressing mode allows us to search the array and activate a subset of processing elements, based on the content of their local memory, rather than their physical address. Subsequent operations then execute only on the active subset of processors. This allows ASProCore to process conditional instructions “in place” without using any additional memory bandwidth.

Each ASProCore Processing Element contains Content Addressable Memory, allowing the programmer to search the entire array in a few clock cycles to identify PEs which match a given criteria, and then activate those processors. Complex search terms such as relational (greater/less than) operators, and min/max functions are implemented as library functions, significantly simplifying the programming model.