The Q Semiconductor IP (SIP) block is a scalable, software-programmable media processing architecture based on our 8th generation ASProCore DSP fabric, optimised for advanced video processing, compression and decoding.

Available for license as a standalone IP core, or as part of a custom platform, the Q core can support a variety of different compression standards, including AVC/H.264 (Baseline, Main & High profiles), Scalable Video Coding (SVC), MPEG-2, MPEG-4 ASP, AVS, Flash, RealVideo, JPEG-2000 and others, via a firmware upgrade.

Scalable to any resolution from QCIF to full 1920x1080p60 HDTV and beyond, the C-programmable architecture acts as a co-processor to any on-chip RISC CPU.

Key features, such as the motion estimation range & strategy, are easily customised at design time or run time to optimise silicon area, video quality, memory bandwidth & power consumption.

The software programmable architecture also allows OEMs to differentiate products by customising algorithms, or by adding advanced video preprocessing techniques.