Based on our 7th generation ASProCore architecture, Linedancer HD processor contains 4,096 processing elements, two 32-bit RISC CPUs, a powerful DMA engine, and a new high-speed streaming data I/O ideal for High Definition video processing and wireless infrastructure applications.
Learn more about Linedancer HD by clicking on different areas of the block diagram:
Twin 32-bit RISC CPU cores
Linedancer HD is programmed using the two on-chip 32-bit RISC CPU cores.
Hardware inter-processor communication and synchronisation mechanisms between the two CPUs are provided to simplify programming. Timer and UART peripherals are also provided.
Each processor has 12KB of cache (8K instruction, 4K data), and all on-chip and off-chip devices can be accessed by either CPU.
The CPUs are supported by a Windows or Linux toolchain, based on the industry-standard GNU compiler. Embedded debug is supported via JTAG, serial ports, or over the PCI-X bus.
A comprehensive set of image and signal-processing libraries are provided to further speed development.
| Note: Information on Linedancer HD is Advance Information. Specifications are subject to change without notice. |
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