Based on our 7th generation ASProCore architecture, Linedancer HD processor contains 4,096 processing elements, two 32-bit RISC CPUs, a powerful DMA engine, and a new high-speed streaming data I/O ideal for High Definition video processing and wireless infrastructure applications.
Learn more about Linedancer HD by clicking on different areas of the block diagram:
Control, GPIO and JTAG ports
A 16-bit synchronous Control interface (multiplexed address/data) is provided on Linedancer HD to interface to an external host CPU or FPGA in an embedded system.
16 bits of General Purpose I/O are also available to either of the RISC CPUs. The GPIO port can also be used to connect an external boot ROM for hostless systems.
A standard JTAG serial port is provided for boundary scan test and embedded debug of Linedancer HD.
| Note: Information on Linedancer HD is Advance Information. Specifications are subject to change without notice. |
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