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Functional Description
Linedancer HD
Overview
Functional Description
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Linedancer HD
Based on our 7th generation ASProCore architecture, Linedancer HD processor contains 4,096 processing elements, two 32-bit RISC CPUs, a powerful DMA engine, and a new high-speed streaming data I/O ideal for High Definition video processing and wireless infrastructure applications.

Learn more about Linedancer HD by clicking on different areas of the block diagram:

DMA Engines (Secondary Data Movement Controllers)

Linedancer HD contains four powerful, independent DMA engines which stream data into and out of the ASProCore array.

Data transfers take place in parallel with the core processing, enabling fully pipelined operation.

Each engine has a bandwidth of up to 1.6 GBytes/second, giving a total bandwidth of up to 6.4 GBytes/second.

Data to be processed, such as frames of digital video, is stored in on-chip or off-chip data memory, which can be expanded up to 4GByte using external DRAM.

The DMA engines have advanced 2D and 3D data transfer modes which can be used to map 2D/3D user data onto the one-dimensional ASProCore array.

Note: Information on Linedancer HD is Advance Information. Specifications are subject to change without notice.

 

 

 
 
 
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